The present invention relates to halftone image recording hardware for controlling a charge flow such as an ion flow for recording halftone images and to a high voltage-resistant circuit that enables such recording hardware to work at high speed.
Some proposals have so far been made of a slit control type of image recorder harnessing corotron discharge in which ions generated by corotron discharge are introduced in a slit and the resulting ion flow is controlled by varying an electric field within the slit wall to form a charge pattern on a recording medium, an aperture control type of image recorder making use of corotron discharge in which ions generated by the corotron are passed through apertures in two control electrodes while controlling an electric field between. The resulting ion flow that goes toward a recording medium is placed under on-off control to form a charge pattern on the recording medium. An aperture control type of image recorder harnesses solid discharge in which high-frequency voltage is applied between electrodes with an insulator located between them to induce discharge, and the resulting ions are selectively drawn by electric field control to form a charge pattern on a recording medium.
In accordance with the image recorders harnessing such an ion flow, the ion flow is constricted by reducing the magnitude of the electric field between the ion flow-control electrodes, making the resulting dot diameter small and, at the same time, giving rise to dot density variations. On the other hand, as the magnitude of the electric field between the electrodes controlling the ion flow increases, there is an increase in the diameter of the ion flow, which concurs with dot density variations. In either case, it is possible to form halftone images by inter-electrode field control. Alternatively, when the application time of the electric field is varied while the magnitude of the electric field between the ion flow-controlling electrodes remains constant, the quantity of charges formed on the recording medium varies and so there is a change in the degree of distortion of the electric field by these charges. Consequently, the resulting latent image potential increases with a dot diameter increase. Here, too, it is possible to form halftone images.
When forming halftone images with a controlled ion flow, it is structurally very difficult to control applied voltage, thereby varying the intensity of the electric field between the control electrodes, because the voltage applied to the electrode for ion flow control is as high as a few hundred volts. By contrast, it is structurally easy to control the voltage-applying time while the voltage applied to the control electrodes remains constant, because this is achieved by making use of pulse width modulation techniques. For this reason, a proposal has been made of image recording hardware making use of such halftone reproduction methods (see JP-A-60-175062 and 61-228771).
Incidentally, when it is intended to carry out halftone reproduction by pulse width control modulation with an aperture control type of image recorder that harnesses solid discharge, the magnitude of latent image potential changes stepwise rather than linearly. This phenomenon will now be explained with reference to FIGS. 1 to 3.
FIG. 1 is a representation for illustrating an aperture control type of image recorder that makes use of solid discharge and is driven by alternating currents.
A recording head shown generally at 1 is built up of a line electrode 1b and an insulator 1c stacked on an insulator 1a in this order. A central aperture is defined by a finger electrode 1d, an insulator 1e and a screen electrode 1f, and a high-frequency power source 5 is connected between the line and finger electrodes 1b and 1d. A signal source 6 is connected between the finger and screen electrodes 1d and 1f for the application of signal voltage. An insulating, recording member 2 provided with an electrode 3 is located in opposition to the recording head 1, and a direct-current power source E is connected between the recording head 1 and the recording member for ion flow acceleration.
This image recorder works as follows. Ion generation is induced by intra-head discharge caused by the application of a high-frequency voltage of a few KV to a few MHz between the line and finger electrodes 1b and 1d. A flow of the resulting ions is controlled in dependence on signal voltage between the finger and screen electrodes 1d and 1f. This signal voltage or, in other words, a pulse width modulation signal is then varied in terms of width t in dependence on signal strength, as shown in FIG. 2 with TO representing the maximum signal width, whereby an electrostatic latent image having halftones is formed on the recording member.
When such a signal of modulated pulse width is furnished to the recording head 1, the potential on the surface of the recording member varies with respect to a pulse width change in a stepwise form, as shown in FIG. 3; in other words, its variation is neither linear nor smooth. To see this, such a sine wave as shown in FIG. 4(a) was used as the high-frequency voltage to the recording head to measure the resulting ion flow. As a result, it was found that, as shown in FIG. 4(b), it is only at the peak of the high-frequency voltage that the ion flow can be detected or, to put it another way, the resulting ion flow is discrete. Even when there was a pulse width change between t1 and t2 that define the positions at which an ion flow is to occur., as shown in FIG. 4(c), there was neither any ion flow nor any change in the surface potential of the recording member--this was true of even when there was a pulse width change. In addition, the moment the pulse width exceeded t2 slightly, there was an ion flow increase, making the surface potential variable in a stepwise form and so making it difficult to obtain variable or high contrast.
So far, the formation of halftone images by use of an ion flow control type of image recorder has relied on voltage amplitude, pulse width or sawtooth wave modulation, but a problem with achieving high-speed driving and high contrast relates to how many halftones are attained for a certain time. That is to say, the determination of what driving speed is applied permits the determination of the time .tau. needed to print one dot. For instance, halftone control must be achieved at a time .tau., when it is intended to reproduce 256 halftones. In this regard, low-speed driving offers no problem, but it is still very difficult to achieve high-contrast expression in the case of high-speed driving. For hardware such an ion printer that works at a few hundred volts, a voltage amplifier circuit of high input impedance and excellent in linearity is usually used so as to amplify halftone image data to a predetermined voltage, and a variety of D-A converters such as those of the resistance and integral types are used as well. However, use of an ordinary voltage amplifier circuit makes it difficult to obtain high voltage as high as a few hundred volts, resulting in some considerable expense. It is also difficult to obtain high-voltage and high-speed outputs having rectangular waves, because the through-rate of the voltage amplifier circuit is not very high. For instance, in the case of a transistor element allowed to have an amplification action, the degree of amplification may be increased by making loading resistance large and current consumption small, but there is a driving speed drop. On the other hand, higher driving speed may be achieved by decreasing loading resistance, but current consumption may be increased with a decrease in the degree of amplification. In short, no tradeoff is achieved between high-speed and low consumption power. In the case of capacitive loading, it is only at a waveform rise or fall time that the output current flows, but currents through loading resistance and transistor elements flow constantly at a high output level, incurring a power consumption increase.
The D-A converters, when built up of ICs, unexceptionally produce only low-voltage output. In addition, when it is intended to set up discrete circuits, such problems as mentioned above arise, usually because of the need of using a voltage amplifier circuit. Conventional or ordinary D-A converters, because of being designed to obtain a continuous form of output, do not lend themselves to ion printers, plasma displays, and so on, for which a discrete, high-voltage rectangular waveform of pulses must be produced. In addition, circuits for driving ion printers, plasma displays, and so on are presumed to work in the form of a parallel array of many identical circuits. To achieve this, however, lower power and lower cost are needed.
Besides, driving circuits with built-in FETs are available for driving ion printers, etc.
FIG. 5 is an illustration of a typical driving circuit using a complementary FET. As illustrated, an N-channel FET 11 and a P-channel FET 12 are connected in series, and 0 V and 15 V, for instance, are added to this series circuit as gate input. Connected to the gate of P-channel FET 12 is a level shifter 13 for converting 0 or 15 V to the on-off control signal level of P-channel FET 12. Then, 0 V and 15 V are alternately fed to the gates of N-channel FET 11 and P-channel FET 12 to put them on and off to achieve low and high-level outputs.
FIGS. 6(a) and 6(b) are illustrations of typical driving circuits using resistance loading. As illustrated in FIG. 6(a), a resistance R is connected to the drain side of an N-channel FET 14. At a gate input of 15 V, FET 14 is put on to produce nothing, whereas at a gate input of 0 V, FET 14 is put off to produce low- and high-level outputs.
FIG. 7 is a typical representation of a totem pole combination of N-channel FETs, in which a buffer is provided to a resistance load type of circuit shown by a broken line in FIG. 6(a). With this circuit, it is possible to obtain a large output current by a buffer 18 and to achieve a sharp rise as well.
FIG. 8 is an illustration of a typical high voltage-resistant driving circuit built up of a series combination of low voltage-resistant P-channel FETs 20 and 21. This circuit is designed to work such that putting P-channel FET 21 off causes P-channel FET 20 to be off, and putting P-channel FET 21 on gives rise to putting P-channel FET 20 on. This circuit is allowed to withstand high voltage because of a series combination of P-channel FETs 20 and 21.
Illustrated in FIG. 5 is a basic driving circuit, but this is unsuitable for a high-voltage driving circuit, because much difficulty is now involved in procuring P-channel FETs having a voltage resistance of 300 V or higher.
The circuit of FIG. 6(a) can work at high speed and at an output waveform fall time, but its rise characteristics are generally not good, because it depends on the value of resistance R and output load, as shown in FIG. 6(b). When the value of R is reduced so as to improve its rise characteristics, there is a current increase when N-channel FET 14 is put on, resulting in a power consumption increase.
The circuit of FIG. 7 is favorable for large capacity loading, but a similar problem as in the resistance loading type circuits of FIGS. 6(a) and 6(b) arises under a capacitive load almost similar to the gate input capacity of an FET. In short, the value of resistance R must be reduced so as to allow N-channel FET 17 to work at high speed, but this results in a power consumption increase.
The circuit of FIG. 8 may be made high-resistant to voltage, because of being built up of a series combination of P-channel FETs, but it cannot work at high speed due to a time constant ascribable to resistance R and the capacities of the FETs. When the value of R is reduced so as to achieve high-speed performance, there is a current increase when N-channel FET 19 is put on, as in the circuits of FIGS. 6(a) and 6(b) only to give rise to a power consumption increase.